In fabrication of semiconductor devices, traditional methods attempting to improve manufacturing yield of an IC design include manual modifications and automated engineering change orders. However, manual modification by an engineer is expensive, slow, and impractical, particularly in large designs having a large number of design improvements to implement. Furthermore, automated engineering change order (ECO) methods are not always feasible, and are frequently invasive. For instance, automated engineering change order methods frequently rip-up one or more nets to improve a manufacturing yield of an IC design and re-route them. However, such rip-up and re-route techniques frequently displace standard-cells, which may cause a degradation in manufacturing yield. Furthermore, such rip-up and re-route techniques modify large portions of an IC design and thus may never converge to a feasible solution and may negatively impact timing and signal integrity of a resulting design, thereby requiring further manual modifications.
A need therefore exists for a methodology enabling an automated improvement of a manufacturing yield of an IC design without a rip-up and re-route of an entire net, and an apparatus for performing the method.